Table of contents
Comparison of the hardware performance
of the AES candidates using reconfigurable hardware
Target FPGA devices: High Performance
Target FPGA devices: Low Cost
Basic building blocks of FPGA devices
Methodology and Tools
Top level block diagram
Basic architecture
Basic architecture: Timing
k-rounds Loop Unrolling
Loop Unrolling: Timing
Loop Unrolling: Speed vs. Area
k-stage Outer-Round Pipelining
Outer-Round Pipelining: Speed vs. Area
Outer-Round Pipelining: Timing
k-stage Inner-Round Pipelining
Inner-Round Pipelininig: Timing
Inner-Round Pipelining: Speed vs. Area
Resuource Sharing
Examples of functions F that can be shared
Performance of alternative architectures:
in non-feedback cipher modes (ECB, counter)
Performance of alternative architectures:
in feedback cipher modes (CBC, CFB, OFB)
Basic architecture: Speed XC 4000XL
Basic architecture: Area XC 4000XL
Basic architecture: Speed Virtex
Basic architecture: Area Virtex
Basic architecture: Speed/Area Virtex
Comparison with results of other groups: Speed
Comparison with results of other groups: Area
Basic architecture of Serpent (encryption)
Serpent architecture with resource sharing
Critical path: Time
Inner-Round Pipelining
Inner-round pipelining: Speed
Choosing optimum architecture for non-feedback cipher modes
Full Mixed Inner and Outer-Round Pipelining
Encryption in non-feedback modes (ECB, counter) decryption in all modes
Need for interleaved operating modes
Encryption in cipher feedback modes
(CBC, CFB, OFB)
Conclusions (1)
Conclusions (2)
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Author: Krzysztof Gaj and Pawel Chodowiec
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