1. electronic version of your source codes submitted through WebCT
2. electronic version of your presentation submitted through WebCT AND brought to the seminar room on a USB memory stick or a CD (floppy disks and zip disks not supported)
3. one printed
copy of your final presentation (6 slides per page) handed to the instructor
before your talk.
Final report without source files (MS Word or PDF format) submitted through WebCT
Names of all team
members
Title of the project
Motivation
general idea of the project and its application
why did you choose this specific project and found it interesting?
Functional specification
1. Function of your arithmetic unit, including
formulas describing unit(s) operation
types and sizes of all operands and results
graphical representation of the input/output interface with names, modes, types, and sizes of all ports
2. Real-life
application of the selected arithmetic unit(s)
Methodology & optimization
3. Optimization
criteria such as
minimum/maximum/limited latency/throughput/area/power
chosen based on the intended application of your design.
4. Short
discussion of the possible architectures and explanation why you have
decided to choose any specific one
5. A detailed block diagram of the architecture of your choice
Tools
6. CAD tools you used, including their exact names and versions, and an
operating system they operated under.
Please, indicate whether you used primarily tools available to you through
- ECE labs,
- ECE server accessed remotely from home,
- machines available to you at work, or
- your computer at home.
Please, specify tools separately for HW and SW.
7. exact hardware
platforms: FPGA device family (optionally, number & standard-cell ASIC library)
Testing
8. Testing procedure, in particular,
methodology for the choice and generation of test vectors
number and types of test vectors
description of the software implementation used to generate test vectors
function of the testbench (short description + pseudocode or a flowchart)
Results
9. Report on the status of your design
A. Overall status (give the percentage in each category):
- written
- verified through functional simulation
- verified through timing simulation
- analyzed for speed & area
e.g.,
- written in 85%
- verified through functional simulation in 80%
- verified through timing simulation in 50%
- analyzed in 25%
B. Status of major functional units
List all major VHDL entities, and evaluate their status in the following
categories (give the percentage in each category)
- written
- verified through functional simulation
- verified through timing simulation
- analyzed for speed & area
Please, support your claims by showing the timing waveforms of your overall
design, or of the highest level unit you verified successfully.
You may use the regular transparencies for that purpose.
10. Results in terms of performance and resource utilization,
including comparative analysis of results obtained using FPGAs and standard-cell ASICs
11. Possible further optimizations
Problems
and conclusions
12. List of
encountered problems & difficulties, and unexplained behavior of your design(s) or design tools
13. Deviations from the original specification (if any), including the percentage of the intended goals achieved
14. Conclusions,
including your satisfaction with the obtained results.
A. Names of all team members
B. Title of the project
C. Introduction & motivation
D. Real-life application of the selected arithmetic unit(s)
E. Function and interface of the arithmetic unit(s)
formulas describing unit(s) operation
types and sizes of all operands and results
control signals
graphical representation of the input/output interface with names, modes, types, and sizes of all ports
table summarizing the meanings of all input/output signals
F. Optimization criteria (must be derived from the analysis of the application described in Section D)
G. Design methodology
considered architectures
justification for the choice of the given architecture
H. Selected architecture
block diagram
short description
I. Test methodology
methodology for the generation of test vectors
number and types of test vectors
description of the software implementation used to generate test vectors
function of the testbench (short description + pseudocode or a flowchart)
J. Language, platform, and tools
hardware description language and/or high-level language used in your project
exact hardware platforms: FPGA device family (optionally, number & standard-cell ASIC library)
exact names and versions of tools used during the project development
K. Final results in terms of performance and resource utilization
L. Discussion of the obtained results
M. Discussion of additional features of your design, such as
regularity (e.g., regular layout with only short local interconnects vs. irregular structure with long interconnects),
scalability (e.g., capability to use one generic code for an arbitrary operand size),
ease of coding (e.g., number of lines of code, ease of determining a pattern of signals and interconnects)
testability (e.g., ease of determining the most critical path in the circuit and values of the corresponding test vectors)
N. List of encountered problems & difficulties, and unexplained behavior of your design(s) or design tools
O. Deviations from the original specification (if any)
P. Conclusions
Q. Comprehensive list of references used in your project (with page numbers in case of books), describing
your intended application
specific HW architecture you have selected to use
specific SW algorithm used to generate test vectors