ECE 645: Spring 2005
Practice Exam I
20 points total
Part I (8 points)
- (1 point) Match the following 5-bit representations
of -12 with the names of these representations:
a. biased with B=24
b. one's complement
c. two's complement
- (1 point) Arrange the following signals in the order
they are generated within the 64-bit 3-level carry lookahead adder, starting
from a signal that is generated first. Assume that the adder is built of AND,
OR, and XOR gates, and that delays of all these gates are equal.
C. g[36, 39]
- (1 point) Arrange the following numbers in the
C. (2 -2 3 -3)4
E. (1 0 -1 1 -1)3
- (1 points) Arrange the following 16-bit adders in
the order of increasing worst case delay. Assume that all adders are built of
AND, OR, and XOR gates, and that the delays of all these gates are equal.
Every adder accepts carry-in and produces carry-out.
- ripple-carry adder
- Kogge-Stone Parallel Prefix Network adder
- Brent-Kung Parallel Prefix Network adder
- 2-level carry-lookahead adder
- 3-level carry-select adder based on short ripple carry
5. (1 point) Determine all outputs of an 8-bit
carry-save adder fed with the following three numbers:
6. (1 point) Using dot notation, show addition of eight
5-bit numbers in the Dadda's tree.
7. (2 points) Compute the product of the following two elements of the
Galois Field GF(28): 'A6' and 'B8'. Assume that an irreducible polynomial P(x)
is equal to P(x)=x8+x4+x3+x+1
Part II (12 points)
(3 points) Using dot notation, show the addition of seven 4-bit
numbers in the Dadda Carry- Save Adder tree. Draw a detailed schematic of the
entire adder corresponding strictly to your dot diagram, using only full
adders, half adders, and NAND gates. Estimate the delay and area of your
circuit, assuming that the full adders and half adders are built of NAND
- (3 points) Design a 16-bit adder using the following
components: 16-input Kogge-Stone parallel prefix network (Parhami, Fig.
6.10) built of NAND gates, supplemented with additional NAND gates. Estimate
the delay and area of this adder expressed in the number of gate levels and
the number of NAND gates respectively.
- (3 points) Determine all bits of the
ANSI/IEEE standard single-precision representation of the following
b. 0 ×infinity
c. -1.234510 / 0
d. -1.0110112 × 2-140
- (3 points) Design a minimum-area 10-bit counter that
counts in steps of 5 starting from 0 to 1000, and then resets itself and
starts counting again. Assume that you can use the following components in
your design: half-adders shown in Parhami, Fig. 5.1, full-adders shown
in Parhami, Fig. 5.2a, and additional NAND gates.