ECE 545
Introduction to VHDL

Fall 2005

Time and location:    Wednesday, 4:30 - 7:10 PM, Innovation Hall, room 133

Instructor:                   Kris Gaj
Email:                         kgaj01@yahoo.com
Office hours:              Monday, 7:30-8:30 PM; Tuesday, 5:30-6:30 PM; Wednesday, 7:30-8:30 PM
                                     S&T II, room 223

TA:                               Shilpa Reddy
Email:                         sreddy2@gmu.edu
Office hours:              Monday, 7:30-9:00 PM, S&T II, room 203
                                     Thursday, 7:30-10:00 PM, S&T I, room 2A

NEW!!! - Introduction to Synopsys - NEW!!!

This is a required course for the Digital Systems Design concentration area
within the MS Program in Computer Engineering.
Apart from teaching VHDL, the course includes also introduction to the state-of-the-art tools
from Aldec, Synplicity, Xilinx, Mentor Graphics and Synopsys.

Please submit all your homework and project reports using WebCT by going to http://webct41.gmu.edu

Please report to the instructor immediately any problems with the access to the Windows server cpe01 or Unix server cpe02, as well as any problems regarding the operation of tools on any machine in the room 203

Required Textbooks

Volnei A. Pedroni, Circuit Design with VHDL, The MIT Press, 2004, ISBN: 0-262-16224-5.

Sundar Rajan, Essential VHDL: RTL Synthesis Done Right, S & G Publishing, 1998.

Supplementary Textbooks

Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 2nd Edition, McGraw-Hill, 2005, ISBN: 0072499389.

Peter J. Ashenden, The Designer's Guide to VHDL, 2nd Edition, San Francisco:Morgan Kaufman, 1996, 2002, ISBN1-55860-674-2 (pbk.), TK7888.3.A863 2002, 621.39'2--dc20

Software Packages Used in This Class

Aldec Active HDL
Synplicity Synplify Pro
Xilinx ISE
Mentor Graphics ModelSim
Synopsys Design Compiler

All software will be available in the FPGA Design Lab, Science & Technology II, room 220.
Some tools, such as ModelSim, can be accessed remotely.

Projects

Specification of Project 1

References for Project 1 - RC6:

RC6 - specification

RC6 - reference implementation in C

RC6 - reference implementation in Java

AESkit - required to run the reference implementation of RC6 in Java

Materials for Project 1 - IIR Filter:

Readme.txt

Coefficients of the 6th order elliptic filter + three inputs and the corresponding outputs

Matlab file used to create all the test signals and to play the results

Plots of the frequency response, pole and zero locations, and the test signals (both inputs and outputs)

NEW!!! - Specification of Project 2 - NEW!!!

NEW!!! - Specification of Project 3 - NEW!!!

Homework

Homework 6, due Friday, October 21

Homework 5, due Wednesday, October 12

Homework 4, due Wednesday, October 5

Homework 3, due Wednesday, September 28

Homework 2, due Wednesday, September 21

Homework 1, due Wednesday, September 14

Viewgraphs

NEW!!! - Lecture 13 - Data Types. Timing in VHDL. - NEW!!!

NEW!!! - Lecture 12 - Behavioral Modeling - The DLX Computer System - NEW!!!

NEW!!! - Source codes for the DLX Computer System - NEW!!!

Lecture 11 - Logic Synthesis with Synopsys

Lecture 10 - Variables, Attributes, Functions and Procedures

Lecture 9 - Timing of Digital Systems

Lecture 7 - Memories: RAM, ROM. Advanced Testbenches.

Xilinx FPGA Memory Library Notes: RAM16X1S, RAM16X1D, RAM32X1S

Lecture 6 - Algorithmic State Machines. Advanced Testbenches. (version with solutions)

Lecture 6 - Sorting Example. (block diagrams and ASM charts)

Lecture 6 - Algorithmic State Machines. Advanced Testbenches. (version without solutions)

Lecture 5 - Finite State Machines. Mixed Style RTL Modeling.

Lecture 4 - Behavioral & Structural Design Styles

Lecture 3a - Introduction to VHDL Simulators: Active HDL and ModelSim (click)

Lecture 3b - Dataflow Modeling of Combinational Logic

Lecture 2 - Introduction to VHDL for Synthesis

Lecture 1 - Organization of the Course and Introduction to the FPGA & ASIC Technologies

Reference Material

VHDL

VHDL Tips & Tricks - a very useful set of slides from the Integrated Systems Laboratory, ETH Zurich

ECE 545 Introduction to VHDL Fall 2005

Time and location: Wednesday, 4:30 - 7:10 PM, Innovation Hall, room 133 Instructor: Kris Gaj Email: kgaj01@yahoo.com Office hours: Monday, 7:30-8:30 PM; Tuesday, 5:30-6:30 PM; Wednesday, 7:30-8:30 PM S&T II, room 223

TA: Shilpa Reddy Email: sreddy2@gmu.edu Office hours: Monday, 7:30-9:00 PM, S&T II, room 203 Thursday, 7:30-10:00 PM, S&T I, room 2A