ECE 545
Introduction to VHDL

Fall 2006

Time and location:    Thursday, 4:30 - 7:10 PM, Innovation Hall, room 209

Instructor:                   Kris Gaj     
Email:                          kgaj@gmu.edu
Office hours:              Wednesday, 7:30-8:30 PM; Thursday, 7:30-8:30 PM
                                     S&T II, room 223

TA:                               Ramakrishna Bachimanchi  
Email:                          rbachima@gmu.edu
Office hours:              Thursday, 7:30-8:30 PM, S&T II, room 203
 

NEW!!! -  Specification of Project 2 - NEW!!!
submission due Tuesday, December 19, noon

Introduction to Synopsys

NEW!!! -  PrimeTime: Static Analysis Tool - scholarly paper by George Michael - NEW!!!
 

Optional Hands-on Sessions for students requiring help with Synopsys tools:
Wednesday, December 13, 2006
Science & Technology II, room 203

6:00-8:00 PM - primarily for students with the last names between Abbott and Malireddy,

 8:00-10:00 PM - primarily for students with the last names between McKinney and York.

PROJECT DEADLINES & EXAM DATES

Example of Project 1 Deliverables from Fall 2005
(see the course web page from Fall 2005 for the Project 1 Specification)

This is a required course for the Digital Systems Design concentration area
within the MS Program in Computer Engineering.
Apart from teaching VHDL, the course includes also introduction to the state-of-the-art tools
from Aldec, Synplicity, Xilinx, Mentor Graphics and Synopsys.

Please submit all your homework and project reports using WebCT by going to http://webct41.gmu.edu

Please report to the instructor immediately any problems with the access to the Windows server cpe01 or Unix server cpe02, as well as any problems regarding the operation of tools on any machine in the room 203

Required Textbooks

Supplementary Textbooks

Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 2nd Edition, McGraw-Hill, 2005, ISBN: 0072499389.

• Aldec Active HDL
• Synplicity Synplify Pro
• Xilinx ISE
• Mentor Graphics ModelSim
• Synopsys Design Compiler

All software will be available in the FPGA Design Lab, Science & Technology II, room 203.
Some tools, such as ModelSim, can be accessed remotely.

Projects

NEW!!! -  Specification of Project 1 (extended Thursday, October 19, 2006) - NEW!!!
 

References for Project 1 - eSTREAM:

eSTREAM PHASE 2 – the ECRYPT Stream Cipher Project

References for Project 1 - FIR:

Z. Mou and P. Duhamel, “Short-length FIR filters and their use in fast nonrecursive filtering,” IEEE Transactions on Signal Processing, vol. 39, no. 6, pp. 1322-1332, June 1991.

NEW!!! - FIR Filter - Matlab code (Windows file encoding) - NEW!!!

NEW!!! - FIR Filter - Matlab code (Unix file encoding) - NEW!!!

Keshab K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, John Wiley & Sons, 1999.
(can be borrowed from the instructor in order to make copies of selected pages)

Uwe Meyer-Baese, Digital Signal Processing with Field Programmable Gate Arrays, 2nd edition, Springer, 2004.
(can be borrowed from the instructor in order to make copies of selected pages)

See Course Webpage from Fall 2005 for the projects from the previous year.

Homework

Homework 5, due Saturday, October 21, midnight

Homework 4, due Thursday, October 12, 4:00 PM

Homework 3, due Sunday, October 1, midnight

Homework 2, deadline extended to Sunday, September 24, midnight

Homework 1, due Thursday, September 14, 4:00 PM

See Course Webpage from Fall 2005 for homework assignments from the previous year.

Viewgraphs

NEW!!! - Source codes for the DLX Computer System - NEW!!!

Lecture 11a - Introduction to Synopsys (hands-on session) (click)

Lecture 11b - Logic Synthesis with Synopsys

Lecture 10 - Variables, Attributes, Functions and Procedures, Data Types

Lecture 9 - Memories: RAM, ROM. Advanced Testbenches. (revised Thursday, November 2, 2006)

Lecture 8b - Sorting Example - Solutions

Lecture 8a - Algorithmic State Machines. Sorting Example.

Lecture 7b - Non-synthesizable VHDL

Lecture 7a - Introduction to FPGA tools for synthesis and implementation

Lecture 6 - FPGA Devices and FPGA Design Flow

Lecture 5 - Finite State Machines

Lecture 4 - Behavioral and Structural Design Styles

Lecture 3b - Dataflow Modeling of Combinational Logic. Simple Testbenches.

Lecture 3a - Introduction to VHDL Simulators: Active HDL and ModelSim (click)

Lecture 2 - Dataflow Modeling of Combinational Logic (covered on September 7, 2006)

Lecture 2 - Introduction to VHDL for Synthesis

Lecture 1 - Organization of the Course and Introduction to the FPGA & ASIC Technologies

Posted gradually one day before a given lecture.

See Course Webpage from Fall 2005 for slides from the previous year.

Reference Material

VHDL

VHDL Instructions: Templates & Examples

VHDL Tips & Tricks - a very useful set of slides from the Integrated Systems Laboratory, ETH Zurich

The Low Carb VHDL Tutorial - by Bryan Mealy

ESA VHDL Modeling Guidelines

Aldec Active HDL

Active HDL Student Edition

ModelSim

ModelSim Survival Guide

Remote Access to ModelSim

Xilinx ISE WebPACK

Xilinx ISE WebPACK - main page

Xilinx ISE WebPACK - FAQ

Synopsys

Introduction to Synopsys

Miscellaneous

Course Webpage from Fall 2005

DLX Support Material

Practice Exams

Midterm Exams from Previous Years

NEW!!! - Midterm Exam 1 from Fall 2005 - NEW!!!

NEW!!! - Midterm Exam 1 from Fall 2004 - NEW!!!

Midterm Exam 2 from Fall 2005

Midterm Exam 2 from Fall 2004
 

Practice Midterm Exams

Practice Exam 1 (all problems except Problem 2)

Practice Exam 2 (all problems except Problem 2)
 

Solutions to the Practice Midterm Exams

Solutions to Practice Exam 1

Solutions to Practice Exam 2