Homework 5

due on Saturday, October 21, midnight

Reading

Xilinx Spartan-3 FPGA Family: Complete Data Sheet

Module 1:  Introduction

• Features

• Architectural Overview

Module 2:  Functional Description

• CLB Overview

• Block RAM Overview

• Dedicated Multipliers

Tools

Please get familiar with the operation and features of at least one environment supporting logic synthesis and implementation targeting Xilinx FPGAs, i.e.,

• Active HDL with Synplify Pro and Xilinx ISE
  AND/OR

• Xilinx WebPack with Xilinx XST and ModelSim Xilinx Edition

In particular, please run

• Integrated Interfaces: Active-HDL with Synplify®

• Integrated Synthesis and Implementation
   

Please use the following documentation as your reference for the Xilinx ISE and Xilinx WebPack software

    Xilinx ISE 8 Software Manuals and Help - PDF Collection

In particular, get familiar with

    ISE Help

    Synthesis and Simulation Design Guide

• Introduction

• General HDL Coding Styles

Coding, simulation, synthesis and implementation

Revise your VHDL codes of the following circuits, developed as a part of your previous homework assignments, to make them fully synthesizable

    Pedroni, Circuit Design with VHDL,

• Problem 6.4: Generic Frequency Divider  (3 points)

• Problem 6.7: Timer #2 (4 points)

• Problem 8.2: Signal Generator #1 (3 points)

• Problem 8.3: Signal Generator #2 (4 points)

For each of these circuits:

• revise the VHDL code, so it gives no errors and no warnings (or at least very few warnings) in synthesis report

• perform post-synthesis simulation

• generate netlist schematic

• perform implementation targeting the smallest device of the Xilinx Spartan 3 family and optimized for minimum area

• perform timing simulation

• perform static timing analysis.

Submit the following documents using WebCT:

• original and revised source codes

• short summary of modifications introduced to the codes

• synthesis report

• netlist schematic

• short summary of implementation reports in terms of resource utilization and timing (seperate text file including: # of CLB slices, # of LUTs, # of FF, #BRAMs, maximum clock frequency, minimum clock period, and slack after a) synthesis, b) mapping, and c) placing & routing);
  please do not submit full implementation reports

• static timing analysis report

• waveforms from timing simulation.

In case of timing waveforms, you can:

save them in an electronic form and submit using WebCT,
OR,
print two pages of the waveforms per each problem, demonstrating the correct operation of the circuit and the presence of logic delays; sign your printouts, and submit them at the beginning of the class following the deadline.