Project HCI-1

Title: Implementation of a selected AES candidate

Description:

The current American encryption standard, DES, has been for a long time considered inadequate to withstand attacks using a specialized cracking machine. This was clearly demonstrated in January 1999, by recovering an unknown DES key in less than 23 hours, using a specialized machine, called Deep Crack, built for about $200,000 by the Electronic Frontier Foundation. A new encryption standard is intended to completely eliminate a threat of such attacks, while providing an algorithm which is faster than DES in both hardware and software. A new standard, referred to as an Advanced Encryption Standard or AES, is being currently selected in a contest organized by the National Institute of Standards and Technology. Fifteen competing algorithms were submitted in June 1998 by research groups from USA, Canada, Japan, Korea, Australia, Israel, Costa Rica, and several European countries. In the first phase of the evaluation process, these algorithms are compared primarily from the point of view of their resistance to known cryptanalitical attacks and the efficiency of their software implementations in C and Java. This phase ended in August 1999 with the selection of five finalists. These limited set of algorithms is further evaluated in terms of their resistance to cryptanalysis, clarity of their design criteria, and their efficiency in hardware. After several months of extensive analysis, some time in the year 2000, a final winner will be selected and later announced as a new Federal Information Processing Standard to replace a venerable DES, and be in use common all over the world for at least several next decades.
You have a unique opportunity to influence this once in a generation selection process by evaluating the efficiency of a selected AES candidate in terms of the efficiency of its hardware implementation. Your task is to develop a VHDL description of the selected algorithm, automatically synthesize it to the gate level, and perform simulations leading to establishing most important timing parameters of your circuit.

Literature:

1. “AES – A Crypto Algorithm for the Twenty-first Century,” available on www at http://csrc.nist.gov/encryption/aes/aes_home.htm
2. Proceedings of the First AES Conference, Ventura, August 1998.
3. Proceedings of the Second AES Conference, Rome, March 1999.
4. Proceedings of the Third AES Conference, New York, April 2000.

Project HCI-2

Description:

IDEA cipher designed in 1990-1992 at ETH in Zurich (European equivalent of MIT) is a possible replacement for the old American standard DES. Bruce Schneier calls IDEA "the best and most secure block algorithm available to the public at this time." The algorithm is already implemented within PGP (Pretty Good Privacy) - an Internet defacto standard for secure mail. The input and output blocks in the IDEA are 64 bit long, while the key is 128-bit long (as compared to 56-bit key in the DES). There are only 3 internal operations of the algorithm, all operating on 16-bit sub-blocks, namely: a) XOR, b) addition modulo 2¹⁶, and c) multiplication modulo 2¹⁶ + 1. Your task is to design and optimize the circuit that implements the IDEA algorithm. The circuit can be implemented as an ASIC or FPGA.

Literature:

1. Ch. Kaufman, R. Perlman, and M. Speciner, "Network Security: Private Communication in a Public World," PTR Prentice Hall, Englewood Cliffs, 1995, pp. 74-79.
2. A. J. Menezes, P. C. van Oorschot, and S. A. Vanstone, "Handbook of Applied Cryptology," chapter 7.6, pp. 263-266.
3. A. Curiger, H. Bonnenberg, R. Zimmerman, N. Felber, H. Kaeslin, and W. Fichtner, "VINCI: VLSI Implementation of the New Block Cipher IDEA," Proc. IEEE CICC'93, San Diego, CA, May 1993, pp. 15.5.1-15.5.4.
4. A. Curiger and B. Stuber, "Specification for the IDEA Chip," Technical Report No. 92/03, Institut fur Integrierte Systeme, ETH Zurich, Feb. 1992.