ECE 449

Computer Design Lab

Spring 2004

Starting with the Spring 1999 semester, the ECE-449 Lab course has been completely revised to incorporate VHDL (Very high speed integrated circuits Hardware Description Language) and XILINX Field Programmable Gate Arrays (FPGA). The course provides practical experience in the design and fabrication of digital circuits. Students learn to write RTL code in VHDL suitable for logic synthesis, simulate their designs at every step of development, and implement them in hardware where final testing is performed.

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Quick Links

• Syllabus
• Experiments
• Lectures
• Literature
• Documentation

Teaching Assistants

Lab/Lecture

Section 203: Tuesday, 4:30-7:10 PM, S&T II, Room 203
Section 201: Thursday, 7:20-10:00 PM, S&T II, Room 203

All students will be provided with an access code to the room 203, and are welcome to work on their experiments at any time.

Course credit:

1 hour

Grading

Lab experiments (Part I):	30%
Midterm Exam:	35%
Lab experiments (Part II):	35%

General Laboratory Rules

• Each lab experiment will be preceded by an introductory lecture and a hands-on session taught by a TA.
   
• Students will be required to demonstrate working experiment and submit both electronic & printed reports during one of the following classes designated as a due date for a particular experiment.
   
• Experiment demonstrations and report submissions will be accepted exclusively during the class time for a particular section.
   
• For each experiment, the demonstration and the report are each worth 50% of points allocated to a given experiment.
   
• Each lab experiment that is late, i.e. not submitted by the end of the class on the designated due date, will be penalized by deducting 1/3 of its allocated points per number of weeks that is late. As a result, no credit will be received for a lab experiment that is more than two weeks late. The additional opportunities will be provided to earn bonus points by completing additional requirements for each experiment or by completing experiment a week or more ahead of schedule. Both penalty and bonus points will apply independently to the demonstrations and to the reports.
   
• Office hours will be devoted to helping students with their experiments and answering any questions related to the subject of the course.
   
• Students are required to work individually on all experiments from Part I of the course, and either individually or in groups of two students on all experiments from Part II of the course. In case of the group work, both students are expected to be intimately familiar with the entire solution to the given experiment and the entire experiment report. This knowledge will be verified during the experiment demonstration and the same grade will be applied to the entire team.
   
• Every completed experiment must be presented to your TA, who will evaluate students results and effort. It is the students' responsibility to convince the TA that their designs work as required. Therefore, students have to simulate and test their designs thoroughly and well document their work. The TA is not required to test anything by himself nor to investigate if the designs are correct in case of insufficient documentation.
   
• In order to prevent cheating and plagiarism, the students will be required to
  - generate a final configuration file in front of the TA during the lab section,
  - submit electronic versions of all source and configuration files at the time of demonstration,
  - answer correctly several detailed questions regarding their experiment solution at the time of demonstration.
  Not complying with either of these requirements may lead to either a total rejection of the demonstration by the TA, or to a substantial reduction of the number of points awarded to the student.
   
• In case of any evident attempt to submit somebody's else work as your own, both students involved in the incident may be penalized by taking away all points for the given experiment. The two repeated attempts to present somebody's else work as your own may lead to the F grade for the entire course, independently of the total amount of points earned by the student before the second incident.
   
• The students are encouraged to help and support each other in all problems related to the
  - operation of the CAD tools,
  - operation of the FPGA boards,
  - operation of the measurement equipment available in the lab,
  - understanding of the problem to be solved during each experiment.
   

The tentative list of experiments

Part I

Experiment 1 - implementing combinational logic in VHDL - 7-segment LED, ALU, etc.

Experiment 2a - implementing sequential logic in VHDL - blinking LEDs (Design & Simulation)

Experiment 2b - implementing sequential logic in VHDL - blinking LEDs, MLU or ALU (Synthesis, Implementation & Testing)

Experiment 3 - description of finite state machines in VHDL - sequence detector

Experiment 4 - description of finite state machines using state editor - pump controller

Hands-on Midterm Exam:

Solutions to the Midterm Exam - Tuesday section

Solutions to the Midterm Exam - Thursday section

Part II

Experiment 5 - programmable pulse generator

Experiment 6 - VGA signal generator

Experiment 7 - microcontroller core

Experiment 7_LA - using logic analyzer

Lecture slides & VHDL codes (to be published before each lecture)

• Introductory lecture by the course coordinator
• Introductory lecture by the course TA
• Lecture 1 - VHDL Refresher & Emphasis On Data Flow
• Lecture 2 - Structural and Behavioral Design Style, Registers, Counters, and Testbenches
• Lecture 3 - Introduction to FPGA Devices, Tools, and Boards
• Lecture 4 - Finite State Machines
• Introduction to Experiment 5 - Programmable Pulse Generator
• Introduction to Experiment 6 - VGA Signal Generator
• Introduction to Experiment 7 - Using Embedded Microcontroller Cores to Implement Complex Digital Systems

Software

Hardware

The XSA-100 FPGA board from XESS Corporation will be used for the experimental verification of students' designs.
The laboratory is equipped with 8 boards of this kind. Students are not required to purchase any boards by themselves.

Recommended textbooks

1. Allen Dewey, Analysis and Design of Digital Systems with VHDL, 1997, PWS publishing, ISBN 0-534-95410-3
2. Sundar Rajan, Essential VHDL: RTL Synthesis Done Right, ISBN 0-9669590-0-0, can be ordered from XESS Corporation Web Site.
3. Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, McGraw-Hill  © 2000 Edition: 1 ISBN: 0072355964.

Useful documentation

1. Tutorials for Active-HDL and Xilinx ISE.
2. Documentation for Xilinx devices, and in particular for the Spartan 2 family.
3. User Manual for the  XSA-100 boards.
4. Xilinx manuals for ISE software.
5. XESS manual for GXSTOOL software.
6. Course web page from Spring 2003.

Maintainer of the page: Kris Gaj