The purpose of this experiment is to introduce you to the description of the Finite State Machines in VHDL that is suitable for logic synthesis. Your task is to implement a FSM (Moore or Mealy) that recognizes all sequences of the form (101)+(11)+ in a long stream of bits. ( )+ means that the sequence inside parentheses has to occur at least once. The circuit receives bits serially and analyzes them on the fly. The diagrams below show Moore and Mealy machines that recognize the sequence. Your task is to write a VHDL code implementing any of those machines.
Perform the following:
- Write a VHDL code representing Moore or Mealy machine given above.
- Write a simple test bench, which will input at least 20 bits to the machine. The input should contain at least three different sequences that should be recognized by the machine.
- Simulate the circuit on the behavioral level using Active-HDL.
- Synthesize the code in Xilinx ISE. Target it to the XC4010XLPC84 device. You may also write your own UCF file, however you are not required to implement it on the XS40 board.
In the lab report include:
- State diagram of the chosen machine.
- Printouts of the VHDL code representing your machine and the test bench.
- Information about resources utilized on the FPGA, which can be found in the map report. How many flip-flops were used to implement this machine? Can you explain where this number came from?
- Output from the functional simulation performed using your test bench. Hint: one page is enough.
| Tuesday | Thursday | |
| Experiment Date | 02/11/2003 | 02/13/2003 |
| Report Due | 02/25/2003 (extended due to snow storm) |
02/20/2003 |
Please email your suggestions to Pawel Chodowiec, Nghi Nguyen or Kris Gaj.