This experiments is mainly an introduction to the CAD tools which will be used throughout the whole semester. Your first task is to simulate and implement a circuit prepared by the instructor. All the files necessary to perform the experiment are available here. This archive should contain:
- lab2.vhd - description of the circuit to implement
- test_lab2.vhd - test bench
- lab2.ucf - User Constraint File
Perform the following:
- Simulate the circuit on the behavioral level using Active-HDL. Change the test bench (only timing issues) so that you will be able to see at least three different combinations of control signals, and observe at least four changes on segments signals per one combination of control signals as shown below.
- Synthesize the code in FPGA Express (Xilinx OEM), or if you get mysterious errors try Synplify PRO. The circuit is going to be run on the FPGA board, therefore target it to the XC4010XLPC84 device. Use the UCF file provided by the instructor.
- Check thoroughly implementation reports. Pay attention to pin allocations.
- Set the clock frequency on the FPGA board to 1MHz.
- Download your bitstream (.bit file) to FPGA board using XESS software.
Reverse engineer the code and identify all components that constitute the circuit. Plot a clear block diagram of this circuit.
Your second task is to design and implement a similar circuit that uses the LED decoder designed during the experiment 1. Implement a 4-bit counter which counts up or down depending on the state of a user input (from a parallel port on the FPGA board). The output of this counter should be decoded by your LED decoder and displayed on the 7-segment LED.
Perform the following:
- Simulate the circuit on the behavioral level using Active-HDL. Your test bench should allow counting up and down for full counting cycle (all 16 values).
- Synthesize the code in FPGA Express (Xilinx OEM), or if you get mysterious errors try Synplify PRO. The circuit is going to be run on the FPGA board, therefore target it to the XC4010XLPC84 device. Prepare your own UCF file with pin allocations according to the XS40 board documentation.
- Check thoroughly implementation reports. Pay attention to pin allocations.
- Set the clock frequency on the FPGA board to 1MHz.
- Download your bitstream (.bit file) to FPGA board using XESS software.
- Your circuit should show counting up and down slow enough to observe it on LED. Make sure to slow down the on-board clock. Use first part of this experiment as a reference.
In the lab report include:
- Block diagram of the circuit given by instructor. This task requires reverse engineering of the VHDL code.
- Short description of your understanding of the circuit operation. Can you compute how fast are the changes on the segments signals when 1MHz clock is applied to the entire circuit?
- Printout of the circuit sourcecode.
- Printout of the test bench that is modified as required.
- Output from the functional simulation performed using your changed test bench. Hint: one page is enough.
- Block diagram of the circuit displaying hex numbers on LED.
- Description of the operation of your circuit.
- Printout of the circuit sourcecode.
- Printout of the test bench that tests your LED circuit.
- Output from the functional simulation for your LED circuit.
| Tuesday | Thursday | |
| Experiment Date | 02/04/2003 | 02/06/2003 |
| Report Due | 02/11/2003 | 02/13/2003 |
Please email your suggestions to Pawel Chodowiec, Nghi Nguyen or Kris Gaj.