• Each lab experiment will be preceded by an introduction and a hands-on session taught by a TA.
   
• The deadlines for submitting all experiment deliverables (including source codes, diagrams, waveforms, configuration files, etc.) are being set as follows:
  
  Tuesday section - Tuesday, 5:30 PM
  Wednesday section - Wednesday, 5:30 PM
  Thursday section - Thursday, 5:30 PM.
   
• Students will be required to demonstrate working experiment during a lab session on a day designated as a due date for a particular lab experiment.
   
• Experiment demonstrations will be accepted exclusively during the class time for a particular lab section.
   
• For each experiment, the demonstration and the electronic deliverables (including lab report) are each worth 50% of points allocated to a given experiment.
   
• Each lab experiment that is late will be penalized by deducting 1/3 of its allocated points per number of weeks that is late. As a result, no credit will be received for a lab experiment that is more than two weeks late. The additional opportunities will be provided to earn bonus points by completing additional requirements for each experiment or by completing experiment a week or more ahead of schedule. Both penalty and bonus points will apply independently to the demonstrations and to the electronic deliverables.
   
• Office hours will be devoted to helping students with their experiments and answering any questions related to the subject of the course.
   
• Students are required to work individually on all experiments from Part I of the course, and either individually or in groups of two students on all experiments from Part II of the course. In case of the group work, both students are expected to be intimately familiar with the entire solution to the given experiment and the entire experiment report. This knowledge will be verified during the experiment demonstration and the same grade will be applied to the entire team.
   
• Every completed experiment must be presented to your TA, who will evaluate students results and effort. It is the students' responsibility to convince the TA that their designs work as required. Therefore, students have to simulate and test their designs thoroughly and well document their work. The TA is not required to test anything by himself nor to investigate if the designs are correct in case of insufficient documentation.
   
• In order to prevent cheating and plagiarism, the students will be required to
  - submit all electronic deliverables by WebCT at the designated time before the experiment demonstration,
  - restrain from any changes in the experiment files in the period between the electronic submission and the experiment demonstration,
  - answer correctly several detailed questions regarding their experiment solution at the time of demonstration.
  Not complying with either of these requirements may lead to either a total rejection of the demonstration by the TA, or to a substantial reduction of the number of points awarded to the student.
   
• In case of any evident attempt to submit somebody's else work as your own, both students involved in the incident may be penalized by taking away all points for the given experiment. The two repeated attempts to present somebody's else work as your own may lead to the F grade for the entire course, independently of the total amount of points earned by the student before the second incident.
   
• The students are encouraged to help and support each other in all problems related to the
  - operation of the CAD tools,
  - operation of the FPGA boards,
  - operation of the measurement equipment available in the lab,
  - understanding of the problem to be solved during each experiment.
   

NEW!!! - Lab 9 - PIC Microcontroller Core. Logic Analyzer. - NEW!!!

Lab 8 - Mixing Handel-C with VHDL. Camera. Image processing in VHDL.

Lab 7 - Introduction to Celoxica DK Design Suite

Lab 6 - Introduction to Musical Sound Generation

Lab 5 - Introduction to VGA Signal Generation

Lab 4 - Finite State Machines

Lab 3 - Introduction to FPGA Board and FPGA Implementation Tools

Lab 2 - Introduction to Synplicity Synplify Pro. Implementing Sequential Logic in VHDL: Grain-128 Stream Cipher.

Lab 1 - Introduction to Aldec Active HDL. Implementing Combinational Logic in VHDL: MLU & mini ALU.

Posted gradually at least one day before a given lab.

See Course Webpage from Spring 2006 for slides from the previous year.
 

VHDL

VHDL Instructions: Templates & Examples
Version 1
Version 2

The Low Carb VHDL Tutorial - by Bryan Mealy

VHDL Tips & Tricks - from the Integrated Systems Laboratory, ETH Zurich
 

FPGAs & FPGA Boards

Introduction to FPGA devices and tools

Documentation for Xilinx devices, and in particular for the Spartan 3 family

Celoxica RC10 FPGA Board User Manual

XESS XSA-3S1000 FPGA Board User Manual

Aldec Active-HDL

Aldec Active-HDL - Getting Started
 

Xilinx ISE

Xilinx manuals for ISE software.

Synopsys

Introduction to Synopsys

Remote Access to Synopsys

Related course web pages

ECE 448 course web page from Spring 2006

ECE 545 course web page from Fall 2006

ECE 449 course web page from Spring 2005

ECE 449 course web page from Spring 2004

ECE 449 course web page from Spring 2003

Exams & Quizzes from Previous Years

Hands-on Midterm Exam from Spring 2004:

Solutions to the Midterm Exam - Tuesday section

Solutions to the Midterm Exam - Thursday section

Hands-on Midterm Exam from Spring 2005:

Solutions to the Midterm Exam - Monday section

Solutions to the Midterm Exam - Tuesday section

Solutions to the Midterm Exam - Thursday section

Practice Midterm Exam from Spring 2006

Practice Hands-on Midterm Exam

Practice Final Exam from Spring 2006

Practice final exam - Parts I & II

Solutions to Practice final exam - Part I

Solution to Part 2 Problem 3 - 2to1mux.vhd, 16to1mux.vhd

Quizzes from Spring 2006

Quiz 1

Quiz 2 with solutions

Quiz 3

Quiz 4 with solutions

Quiz 5 with solutions

Final Exam from Spring 2006

Final Exam Part I - version 1

Final Exam Part II - version 1

Final Exam Part I - version 2

Final Exam Part II - version 2