---------------------------------------------------------------------------------------------------
--
-- Title       : 16to1mux
-- Design      : MidTerm
-- Author      : Kamal Sayeed
-- Company     : George Mason University
--
---------------------------------------------------------------------------------------------------
--
-- File        : Th_problem3_16to1mux.vhd
-- Generated   : Sun Mar  7 20:58:44 2004
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
---------------------------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Midterm_p3 is
	 port(
		 Input  : in STD_LOGIC_VECTOR (0 to 15);
		 sel    : in STD_LOGIC_VECTOR (3 downto 0);
 		 output : out STD_LOGIC 
	     );
end Midterm_p3;

architecture Mux_16to1_DF of midterm_p3 is		  

signal Mux_out1:std_logic_vector (0  to 7);
signal Mux_out2:std_logic_vector (0  to 3);
signal Mux_out3:std_logic_vector (0  to 1);
----------------------------------------------------------------------------------
COMPONENT Mux_2to1 is PORT (input1, input2, sel :in std_logic;
		                    output		 	    :out std_logic
                          );
end component Mux_2to1;	 
------------------------------------end of component declaration-----------------
begin			
	G1: for i in 0 to 7 generate
		Mux_array1: Mux_2to1 port map(input(2*i), input(2*i+1), sel(0), Mux_out1(i));
	end generate;


	G2: for i in 0 to 3 generate
		Mux_array2: Mux_2to1 port map(Mux_out1(2*i), Mux_out1(2*i+1), sel(1), Mux_out2(i));
	end generate;
	

	G3: for i in 0 to 1	generate
		Mux_array3: Mux_2to1 port map(Mux_out2(2*i), Mux_out2(2*i+1), sel(2), Mux_out3(i));
    end generate;
	
lastmux:Mux_2to1 port map(Mux_out3(0), Mux_out3(1), sel(3), output);
	
end Mux_16to1_DF ;