Home page of Prof. K. J. Hintz with office room number, office hours, and contact information.

Thursday, 1630-1910, Innovation Hall, Room 207 and Lab, Room 203, S&T-II.

3 hours

Makeup exams are rarely given. Requests for a delayed Final Exam due to multiple tests (>2) in one day will ONLY be considered if proper forms are completed and in my hands prior to the mid-semester break.

If you need special assistance, please inform me soon so that we can work something out.

Attendance at lectures and laboratory is not graded but expected.

You are encouraged to collaborate with other students on homework, and labs. The normal honor code applies to all tests and exam problems and programming projects.

	Midterm: 35%  (1/2 in class, 1/2 take-home VHDL problem)
	Final Exam: 40% (The final exam may be replaced by a significant semester-long project on an individually negotiated basis.  There will be no incompletes.)
	Homework: 25%

Homeworks (see button at top of page) are due the week after the applicable chapter is covered in class. Late homeworks will receive a maximum of 1/2 credit.

Weekly milestones

There will be a midterm and a final examination, both of which will be closed book, closed notes.

Fall 2001 MidTerm Exam (coding portion):  Here is a typical midterm exam problem along with an acceptable solution.  The solution is included here to provide you with examples (f1_tc.pdf and spd_sensor.pdf ) of the expected level of coding discipline and compliance with the ESA coding standards for all homeworks and the examinations.  Here is an example of an acceptable testbench for the problem.   Here are two other testbenches based on homework problems.

Fall 2001 Final Exam: The following files are made available for your use on the final examination, Fall 2001.  Be sure that your examination solution (filename:  pl3_if.vhd) has the same pinouts as the testbench.

    PL3 Interface TestBench:  p13_if_tb.vhd

    Updated PL3 Interface TestBench: p13_if_tb_2.vhd

    Packet FIFO Component instantiated in TB above: packet_fifo.vhd

The final exam (2001) will have a problem based on the implementation of a subset of the ATM specification which can be found at ftp://ftp.atmforum.com/pub/approved-specs/af-phy-0143.000.pdf.   Understanding the entire specification is not required or even necessary for the exam.  This reference is listed for those who are interested in the background of the previous final examination problem.

Fall 2002 Final Exam:  The final exam will be distributed in hardcopy in class.  You will know that you have solved the problem correctly when your code passes the testbench for the final examination.  Some of your work has already been done in these utilities which are required for the testbench to work properly.

Fall 2003 Final Exam (revised student package posted, 12/5/03, 10:50):  The final exam has been distributed electronically.  You will know that you have solved the problem correctly when your code passes the testbench for the final examination.  Some of your work has already been done in these utilities which are required for the testbench to work properly.

Required text

Ashenden, Peter J., The Designer's Guide to VHDL, 2nd Edition, San Francisco:Morgan Kaufman, 1996, ISBN1-55860-674-2 (pbk.), TK7888.3.A863 2002, 621.39'2--dc20

IEEE Interactive VHDL Tutorial is available for purchase from IEEE on CDROM. There are versions available for Sun and PCs. This tutorial is locally available on-line, but password protected.   Access instructions will be distributed in class.

	The centerpiece of the course will be the VHDL simulation software, particularly ModelSim, donated to GMU. This donation of approximately $621,000 of MGC software was received December, 1996. The software can be accessed  by students registered in this and other courses via the internet from off-campus.
	Information on getting your account set up to use Mentor Graphics tools can be found   at VHDL Resources.